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ADM1026
Table 4. ELECTRICAL CHARACTERISTICS (T A = T MIN to T MAX , V CC = V MIN to V MAX , unless otherwise noted. (Note 1, 2, and 3))
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SERIAL BUS TIMING
Start Hold Time, t HD; STA
SCL Low Time, t LOW
SCL High Time, t HIGH
SCL, SDA Rise Time, t r
SCL, SDA Fall Time, t f
Data Setup Time, t SU; DAT
Data Hold Time, t HD; DAT
4.0
4.7
4.0
?
?
250
300
?
?
?
?
?
?
?
?
?
?
1000
300
?
?
m s
m s
m s
ns
ns
ns
ns
1. All voltages are measured with respect to GND, unless otherwise specified.
2. Typicals are at T A = 25 ? C and represent the most likely parametric norm. Shutdown current typ is measured with V CC = 3.3 V.
3. Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.1 V for a rising edge.
4. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. V BAT is accurate
only for V BAT voltages greater than 1.5 V (see Figure 14).
5. Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms ? 11.38 ms measurements on analog input and internal
temperature channels, and 2 ms ? 34.13 ms measurements on external temperature channels.
6. The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number
of fans connected and the fan speed. See the Fan Speed Measurement section for more details.
7. ADD is a three-state input that may be pulled high, low, or left open circuit.
8. Logic inputs accept input high voltages up to 5.0 V even when device is operating at supply voltages below 5.0 V.
9. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at ? 40 ? C, +25 ? C, and +85 ? C. Typical endurance
at +25 ? C is 700,000 cycles.
10. Retention lifetime equivalent at junction temperature (T J ) = 55 ? C as per JEDEC Std. 22 method A117. Retention lifetime based on activation
energy of 0.6 V derates with junction temperature as shown in Figure 15.
t LOW
t R
t F
t HD; STA
SCL
t HD; STA
t HD; DAT
t HIGH
t SU; DAT
t SU; STA
t SU; STO
SDA
P
t BUF
S
S
P
Figure 2. Serial Bus Timing Diagram
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